1. Field of the Invention
This invention relates to the field of memory circuits. More particularly, this invention relates to memory array read circuitry.
2. Description of the Prior Art
In known memory systems a pair of complementary bit-lines is configurable to be selectively chargeable such that the pulling down of a voltage of one of the pair of complementary bit-lines corresponds to a logic value of one whereas the pulling down voltage of the other one of the pair of complementary bit-lines corresponds to a logic value zero. During a memory read operation both of the pair of complementary bit-lines are precharged to a high voltage and an associated wordline is asserted (activating a row of memory cells). One of the two bit-lines is pulled down in dependence upon the data value stored in an associated memory cell. The speed of pull down of the bit-lines has an influence on the speed of operation on the memory. It is known to increase the rate at which a bit-line is pulled down and to increase the speed of a read operation by providing a pull-down circuit to pull-down the voltage of the pair of bit-lines. However, if the strength of the pull-down device is too strong then errors in the read operations can occur whereas if the pull-down circuit is too weak then the memory is not likely to reach its fill speed potential and lack of efficiency results.
Accordingly there is a need for a more efficient system for performing pull down of bit-lines during read operations i.e. a system capable of properly balancing the requirement for increasing speed of memory operation against the risk of increasing the number of fails in read operations due to a pull-down circuit that is too strong. Providing such a system is made more difficult by the different requirements with regard to the strength of pull-down associated with different memory cells and different memory types.